1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive structures, such as conductive lines and vias, using a dual hard mask integration technique.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc.
In modern ultra-high density integrated circuits, device features have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, commensurate with the ongoing shrinkage of feature sizes, certain size-related problems arise that may at least partially offset the advantages that may be obtained by simple size reduction alone. In general, decreasing the size of, for instance, circuit elements, such as MOS transistors and the like, may lead to superior performance characteristics due to a decreased channel length of the transistor element, thereby resulting in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as conductive lines and contact vias and the like—that may fit within the available real estate. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is similarly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements. Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices.
FIGS. 1A-1B depict one illustrative prior art technique for forming conductive structures, such as metal lines, in a layer of insulating material. FIG. 1A depicts a portion of an illustrative metallization layer 10 of an integrated circuit product wherein conductive structures will be formed to establish electrical connection to underlying devices (not shown), such as transistors, capacitors, etc. At the point of fabrication depicted in FIG. 1A, several process operations have been performed. For example, various semiconductor devices (not shown), e.g., transistors, have been formed in and above a semiconducting substrate (not shown). A typical integrated circuit product contains multiple metallization layers. The illustrative metallization layer 10 may be formed at any level of the integrated circuit device.
In the illustrative example depicted in FIG. 1A, the metallization layer 10 is comprised of a cap layer 12, such as NBLOK, a layer of insulating material 14, a metal hard mask layer 18, such as titanium or titanium nitride, and a metal material 22 that is formed in trenches 20 that were formed in the layer of insulating material 14. The metal material 22 is representative in nature in that it may include one or more barrier layers, which are not depicted in FIG. 1A. The various layers of material depicted in FIG. 1A may be comprised of a variety of different materials and they may be formed by performing a variety of known deposition processes. The trenches 20 maybe be formed using known photolithographic and etching tools and techniques. However, by virtue of the etching processes performed in forming the trenches 20, there is a slight outwardly tapered surface 23 of the layer of insulating material 14 proximate the upper surface of the layer of insulating material 14.
As shown in FIG. 1B, a chemical mechanical polishing (CMP) process has been performed to remove the excess metal material 22 positioned outside of the trenches 20 in the layer of insulating material 14 to thereby define conductive structures 22A. However, due to the tapered surface 23 that was formed when forming the trenches 20, the conductive structures 22A exhibit outwardly flared regions 24 that effectively reduce the distance 25 between adjacent conductive structures 22A. Since spacing between adjacent conductive structures in modern integrated circuit devices is already very limited due to high packing density requirements, the flared regions 24 on the conductive structures 22A can be problematic for several reasons. For example, the reduction in separation between adjacent conductive structures due to the presence of the flared regions 24 can lead to many voltage-related dielectric breakdown problems, such as reduced device performance due to an undesirable increase in cross-talk and, in a worst case scenario, electrical shorts which can lead to complete device failure.
The present disclosure is directed to various methods of forming conductive structures using a dual hard mask integration technique that may solve or at least reduce one or more of the problems identified above.